This invention relates to nonvolatile semiconductor memory devices and, more particularly, to flash electrically erasable, programmable, read-only memories (flash EPROMs) having floating-gate-type memory cells and, more particularly to a method of making such devices on a chip while at the same time making digital control circuitry.
An array structure using buried diffusion wells (tanks) is described in U.S. Pat. No. 5,411,908 issued May 2, 1995, and entitled “FLASH EEPROM ARRAY WITH P-TANK INSULATED FROM SUBSTRATE BY DEEP N-TANK”. That patent is assigned to Texas Instruments Incorporated.
The prior-art includes programming and erasing floating-gate memory cells by Fowler-Nordheim tunneling. During flash erasure of floating-gate cells by Fowler-Nordheim tunnelling, the substrate and control gates (wordlines) of each cell are typically connected to 0V, the sources (source lines) of each cell are connected to a positive voltage of perhaps +10V to +15V, and the drains (bitlines) are allowed to float (connected to a high impedance). In the prior-art, tunnelling areas are usually formed between the floating gate and a double-diffused source extending under the floating gate, but separated from the floating gate by a thin gate insulator. In other cases, tunneling occurs in a window having a thin insulator formed at or near the source.
When using a double-diffused tunnel, the source of each cell is typically formed by an arsenic doping at the same time the drain is doped, followed by a separate mask and phosphorus doping steps, followed by a driving anneal step that causes the phosphorus of the source diffusion to expand under the floating gate to form a tunnelling region. As a result, the floating gate must have sufficient length that the phosphorus diffusion of the source does not reach through (punch-through) to the drain.
The positive voltage applied to the sources (source lines) during erase reverse-biases the P-N junction formed at the N-type source diffusion of each cell and the P-type substrate. The reverse-bias voltage is the cause of undesirable cell-breakdown-voltage problems during flash erase. The cell-breakdown problem is sometimes referred to as the field-plate breakdown of the source to the substrate during erase. The same cell-breakdown problem occurs if a sufficiently large reverse voltage is applied to the drain diffusion.
U.S. Pat. NO. 4,924,437 issued May 8, 1990, also assigned to Texas Instruments Incorporated, describes a Fowler-Nordheim method of programming a cell by applying a pulse of about −8V to the control gate together with about +5V applied to the source. While in the majority of nonvolatile-memory-array types, erased cells have floating gates with a neutral or almost neutral charge, in that example erased cells have negatively charged floating gates.
A flash memory using negative wordline erase and triple-well CMOS technology is described in “A 5-V-Only 16-Mb Flash Memory with Sector Erase Mode” by Toshikatsu Jinbo, et al., in Vol. 27, No. 11 of The Journal of Solid-State Circuits, November, 1992 at pages 1547-1553. The array described in that article ha sources of “H-type” cells, sometimes called “NOR” cells, (see FIG. 2 of the article) connected to a common node. Each “H-type” cell has a drain implant (see FIG. 3 of the article) for the purpose of lowering the voltage required for hot-carrier-injection programming. Manufacture of the cells described in the article requires extra masking steps that are unnecessary for constructing a usable nonvolatile memory with control logic circuitry using the minimum number of masking steps. “H-type” cells are relatively large when compared to the size of cells, such as “X-type” cells. “X-type” cells are described, for example, in U.S. Pat. No. 4,281,397 issued Jul. 28, 1981, also assigned to Texas Instruments Incorporated. In the past, “X-type” cells have been limited to use in ultraviolet-erasable EPROMs. However, one of the advantages of “X-type” nonvolatile cells is that such cells may be scaled down in size with ongoing improvements in lithographic and processing techniques.
U.S. Pat. No. 5,299,162 issued to Kim et al. on Mar. 29, 1994 describes erasing to negative-threshold-voltage of a selected NAND-type nonvolatile cell by applying 20V to the substrate, source and drain with 0V on the control gate.
There is a need for a nonvolatile-memory array/cell structure that is constructed simultaneously with logic circuitry on the same chip. Such a structure is, for example, useful for controlling data flow into and out of a large-capacity hard-disk drive. Other applications include combination microcontroller/data-storage devices such as electronic cameras, answering machines, and automatic control devices of all kinds. Preferably the cell structure of the memory should use a minimum amount of space, yet be scalable along with the logic structure to take advantage of smaller photolithographic geometries as those capabilities become available. The cell area should be as small as the very small area required by ultraviolet-erasable EPROM cells. In addition, the cell structure should eliminate the problem of field-plate breakdown during flash erase. For flexible application, the memory should be flash-erasable line-by-line using positive voltages.